View AD1881_127834.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
AC'97 2.1 FEATURES Variable Sample Rate True Line-Level Output Supports Secondary Codec Modes
AC'97 SoundMAX(R) Codec AD1881A
ENHANCED FEATURES Mobile Low Power Mixer Mode Digital Audio Mixer Mode Full Duplex Variable 8 kHz to 48 kHz Sampling Rate with 1 Hz Resolution PHATTM Stereo 3D Stereo Enhancement Split Power Supplies (3.3 V Digital/5 V Analog) Extended 6-Bit Master Volume Control Audio Amp Power-Down Signal
AC'97 FEATURES Designed for AC'97 Analog I/O Component 48-Lead LQFP Package Multibit Converter Architecture for Improved S/N Ratio Greater than 90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for Connection from LINE, CD, VIDEO, and AUX Two Analog Line-Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input Switchable from Two External Sources High Quality CD Input with Ground Sense Stereo Line-Level Output Mono Output for Speakerphone or Internal Speaker Power Management Support FUNCTIONAL BLOCK DIAGRAM
CS0 CS1 EAPD
MODE
AD1881A
MODE/SYNCHRONIZER
MIC1 MIC2 LINE_IN
0dB/ 20dB
CD VIDEO PHONE_IN
SELECTOR
AUX
PGA
16-BIT A/D CONVERTER
PGA
16-BIT A/D CONVERTER
RESET
SYNC MONO_OUT MV G A M G A M G A M G A M G A M G A M
AC LINK
SAMPLE RATE GENERATORS
BIT_CLK
LNLVL_OUT_L
SDATA_OUT
POP
LINE_OUT_L
MV
D A M
PHAT STEREO
NC
G A M
16-BIT D/A CONVERTER
SDATA_IN
LINE_OUT_R
MV
POP
PHAT STEREO
NC
G A M
16-BIT D/A CONVERTER
LNLVL_OUT_R A M PC_BEEP
G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME NC = NO CONNECT
OSCILLATORS
XTL_OUT
XTL_IN
SoundMAX is a registered trademark and PHAT is a trademark of Analog Device, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD1881A-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal 25 3.3 5.0 48 1008 C V V kHz Hz DAC Test Conditions Calibrated -3 dB Attenuation Relative to Full-Scale Input 0 dB 10 k Output Load ADC Test Conditions Calibrated 0 dB Gain Input -3.0 dB Relative to Full-Scale
ANALOG INPUT
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP MIC with +20 dB Gain (M20 = 1) MIC with 0 dB Gain (M20 = 0) Input Impedance* Input Capacitance*
MASTER VOLUME
Min
Typ 1 2.83 0.1 0.283 1 2.83 20 5
Max
Unit V rms V p-p V rms V p-p V rms V p-p k pF
7.5
Parameter Step Size (0 dB to -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size (0 dB to -46.5 dB); MONO_OUT Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental*
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ 1.5 -94.5 1.5 -46.5
Max
Unit dB dB dB dB dB
80
Parameter Step Size (0 dB to 22.5 dB) PGA Gain Range Span
ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS
Min
Typ 1.5 22.5
Max
Unit dB dB
Parameter Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC Step Size (0 dB to -45 dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
*Guaranteed, not tested. Specifications subject to change without notice.
Min
Typ 90 90 1.5 -46.5 3.0 -45
Max
Unit dB dB dB dB dB dB
-2-
REV. 0
AD1881A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
Min 0 0.4 x FS 0.6 x FS -74
Typ
Max 0.4 x FS 0.09 0.6 x FS
Unit Hz dB Hz Hz dB sec s
12/FS 0.0
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ 16
Max 0.02 -74
Unit Bits % dB dB dB dB dB % dB mV
87 85 -100 -90 -90 -85 10 0.5 10.5
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT, LNLVL_OUT Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy (Measured from 0.6 x FS to 20 kHz)*
ANALOG OUTPUT
Min
Typ 16
Max 0.02 -74
Unit Bits % dB dB dB % dB dB dB
90 85 10
0.7 -80
-40
Parameter Full-Scale Output Voltage (LINE_OUT, LNLVL_OUT) Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance VREF VREF_OUT Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
*Guaranteed, not tested. Specifications subject to change without notice.
Min
Typ 1 2.83
Max
Unit V rms V p-p k pF pF V V mV
500 10 15 2.0 2.2 2.2 5 100 2.5
REV. 0
-3-
AD1881A-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter High Level Input Voltage (VIH ): Digital Inputs Low Level Input Voltage (VIL ) High Level Output Voltage (VOH ), IOH = -0.5 mA Low Level Output Voltage (VOL ), IOL = +0.5 mA Input Leakage Current Output Leakage Current
POWER SUPPLY
Min 0.65 x DVDD 0.9 x DVDD -10 -10
Typ
Max 0.35 x DVDD 0.1 x DVDD +10 +10
Unit V V V V A A
Parameter Power Supply Range - Analog Power Supply Range - Digital (3.3 V) Power Dissipation - 5 V/3.3 V Analog Supply Current - 5 V Digital Supply Current - 3.3 V Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS*
Min 4.75 3.0
Typ
Max 5.25 3.6
Unit V V mW mA mA dB
280 40 23 40
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN MODE
Min 45
Typ
Max
Unit MHz %
24.576 50 55
Parameter ADC DAC ADC and DAC ADC + DAC + Mixer (Analog CD On) Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Analog CD Only (AC-Link On) Analog CD Only (AC-Link Off) Standby
*Guaranteed, not tested. Specifications subject to change without notice.
Set Bits PR0 PR1 PR1, PR0 LPMIX, PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 LPMIX, PR5, PR1, PR0 LPMIX, PR1, PR0, PR4, PR5 PR5, PR4, PR3, PR2, PR1, PR0
DVDD (3.3 V) Typ 17 17 4 4 20 17 17 4 4 0 0
AVDD (5 V) Typ 30 26 20 12 18 12 8 2 12 12 0.1
Unit mA mA mA mA mA mA mA mA mA mA mA
-4-
REV. 0
AD1881A
TIMING PARAMETERS 1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter2 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay (ATE Test Mode) Propagation Delay RESET Rise Time
NOTES 1 Guaranteed, not tested. 2 Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 50
Typ 833
Max
Unit ns s ns s ns MHz ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns
80 19.5 162.8 12.288 81.4 36.62 36.62 40.69 40.69 48.0 20.8 2.5 4 4 4 4 4 4 4 4 750 44.76 44.76
5 5 2 2 2 2 2 2 2 2 0 15
10 10 10 10 10 10 10 10 10 25 15 50
REV. 0
-5-
AD1881A
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure 1. Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT 1
SLOT 2
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE TO 0x26
DATA PR4
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
SDATA_IN
tS2_PDOWN
NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
-6-
REV. 0
AD1881A
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (VDD) Analog (VCC) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
Min -0.3 -0.3 -0.3 -0.3 0 -65
Max +3.6 +6.0 VCC + 0.3 VDD + 0.3 +70 +150
Unit Model V V V V C C
Temperature Range
Package Description 48-Lead LQFP
Package Option ST-48
AD1881AJST 0C to 70C
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package LQFP
JA JC CA
76.2C/W
17C/W
59.2C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1881A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION 48-Lead LQFP
EAPD/CHAIN_IN
LNLVL_OUT_R NC
LNLVL_OUT_L
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 PC_BEEP 12
13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 IDENTIFIER
AVDD2
MODE
CS1
MONO_OUT
36 LINE_OUT_R 35 LINE_OUT_L 34 CX3D 33 RX3D 32 FILT_L 31 FILT_R 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AV DD1
CS0
AD1881A
TOP VIEW (Not to Scale)
PHONE_IN AUX_L
NC NC
AVSS2
MIC1
MIC2
CD_GND_REF
NC = NO CONNECT
REV. 0
-7-
LINE_IN_R
VIDEO_R CD_L
AUX_R
CD_R
LINE_IN_L
VIDEO_L
AD1881A
PIN FUNCTION DESCRIPTIONS
Digital I/O
Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET
LQFP 2 3 5 6 8 10 11
I/O I O I O O I I
Description Crystal (or Clock) Input, 24.576 MHz. Crystal Output. AC-Link Serial Data Output, AD1881A Input Stream. AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy Chain Output Clock. AC-Link Serial Data Input. AD1881A Output Stream. AC-Link Frame Sample Sync 48 kHz Fixed Rate. AC-Link Reset. AD1881A Master H/W Reset.
Miscellaneous Connections
Pin Name CS0 CS1 EAPD MODE
Analog I/O
LQFP 45 46 47 48
I/O I I O I
Description Chip Select 0. Chip Select 1. External Amp Power-Down Control Signal, Default LO, Active HI MODE Select.
These signals connect the AD1881A component to analog sources and sinks, including microphones and speakers. Pin Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT LNLVL_OUT_L LNLVL_OUT_R
Filter/Reference
LQFP 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 41
I/O I I I I I I I I I I I I I O O O O O
Description PC Beep. PC Speaker Beep Passthrough. Phone. From Telephony Subsystem Speakerphone or Handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. Video Audio Left Channel. Video Audio Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Pseudo-Differential CD Input. CD Audio Right Channel. Microphone 1. Desktop Microphone Input. Microphone 2. Second Microphone Input. Line In Left Channel. Line In Right Channel. Line Out Left Channel. Line Out Right Channel. Monaural Output to Telephony Subsystem Speakerphone. Line-Level Output Left Channel. Line-Level Output Right Channel.
These signals are connected to resistors, capacitors, or specific voltages. Pin Name VREF VREFOUT AFILT1 AFILT2 FILT_R FILT_L RX3D CX3D LQFP 27 28 29 30 31 32 33 34 I/O O O O O O O O I Description Voltage Reference Filter. Voltage Reference Output 5 mA Drive (Intended for MIC Bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. AC-Coupling Filter Capacitor--ADC Right Channel. AC-Coupling Filter Capacitor--ADC Left Channel. 3D PHAT Stereo Enhancement--Capacitor. 3D PHAT Stereo Enhancement--Capacitor.
-8-
REV. 0
AD1881A
Power and Ground Signals
Pin Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2
No Connects
LQFP 1 4 7 9 25 26 38 42
Type I I I I I I I I
Description Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND
Pin Name NC NC NC
LQFP 40 43 44
Type
Description No Connect No Connect No Connect
MIC1 MIC2
0 MS 1 0x20
0dB/20dB M20 0x0E
LS/RS (0) LS (4) RS (4) GM 0x1C LIM LS (3) IM RS (3) LS (1) RS (1) LS (2) RS (2)
AD1881A
LINE_IN
AUX CD VIDEO PHONE_IN
STEREO MIX (L) MONO MIX STEREO MIX (R)
MONO_OUT
GM 0x1C LS/RS (7) RIM LS (5) IM LS/RS (6) RS (5)
S E L E C T O R
GM 0X1C RIM IM
16-BIT A/D
0X74
GM 0X1C LIM IM
16-BIT A/D
RESET
MV
MIX 0x20
GA 0x0C PHV M 0x0C PHM M 0x0E MCM M 0x10 LM M 0x16 CM M 0x12 AM M 0x14 VM GA 0x0E GA 0x10 MCV LLV RLA GA 0x16 LCV RCV GA 0x12 LAV RAV GA 0x14 LVV RVV
S 0x1A
SYNC
PCM DAC RATE 0x2C SR1 0x7A PCM ADC RATE 0x32 SR0 0x78
LPBK 0x20
AC LINK
BIT_CLK
SDATA_OUT
LNLVL_OUT_L
SDATA_IN 0x02 MM 02 LMV 0x22 DP POP 0x20 GAM 0x18 LOV OM
NC
LINE_OUT_L
PHAT 0x20
16-BIT D/A
DAM
LINE_OUT_R
0x02 MM
02 LMV
0x22 DP POP 0x20
PHAT 0x20
0x20 POP NC
GAM 0x18 ROV OM
16-BIT D/A
LNLVL_OUT_R
M 0x0A PCM A 0x0A G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME
PC_BEEP
PCV
OSCILLATORS
XTL_OUT
XTL_IN
Figure 8. Block Diagram Register Map
REV. 0
-9-
AD1881A
PRODUCT OVERVIEW Analog-to-Digital Signal Path
The AD1881A meets the Audio Codec '97 2.0 and 2.1 Extensions. In addition, the AD1881A SoundMAX Codec is designed to meet all requirements of the Audio Codec '97, Component Specification, Revision 1.03, (c) 1996, Intel Corporation, found at www.Intel.com. The AD1881A also includes some other Codec enhanced features such as the built-in PHAT Stereo 3D enhancement. The AD1881A is an analog front end for high performance PC audio applications. The AC'97 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer and I/O. The main architectural features of the AD1881A are the high quality analog mixer section, two channels of ADC conversion, two channels of DAC conversion with Data Direct Scrambling (D2S) rate generators. The AD1881A's left channel ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.
FUNCTIONAL DESCRIPTION
The selector sends left and right channel information to the programmable gain amplifier (PGA). The PGA following the selector allows independent gain control for each channel entering the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each channel of the ADC is independent, and can process left and right channel data at different sample rates.
Sample Rates and D2S
The AD1881A default mode sets the Codec to operate at 48 kHz sample rates. The converter pairs may process left and right channel data at different sample rates. The AD1881A sample rate generator allows the Codec to instantaneously change and process sample rates from 8 kHz to 48 kHz with a resolution of 1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below -90 dB. The AD1881A uses a 4-bit D/A structure and Data Directed Scrambling (D2S) to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device's quantization noise floor. The D2S process pushes noise and distortion artifacts caused by errors in the multibit DAC to frequencies beyond the auditory response of the human ear and then filters them.
Digital-to-Analog Signal Path
This section overviews the functionality of the AD1881A and is intended as a general introduction to the capabilities of the device. Detailed reference information may be found in the descriptions of the Indexed Control Registers.
Analog Inputs
The Codec contains a stereo pair of ADCs. Inputs to the ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo CD ROM (CD), stereo audio from a video source (VIDEO) and post-mixed stereo or mono line output (LINE_OUT).
Analog Mixing
The analog output of the DAC may be gained or attenuated from +12 dB to -34.5 dB in 1.5 dB steps, and summed with any of the analog input signals. The summed analog signal enters the Master Volume stage where each channel of the mixer output may be attenuated from 0 dB to -94.5 dB in 1.5 dB steps or muted.
Line-Level Outputs
The AD1881A offers a true line-level output for notebook docking station and home theater applications. The line-level output does not change with master volume settings.
Host-Based Echo Cancellation Support
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD and VIDEO can be mixed in the analog domain with the stereo output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB to -34.5 dB in 1.5 dB steps. The summing path for the mono inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT) duplicates mono channel data on both the left and right LINE_OUT. Additionally, the PC attention signal (PC_BEEP) may be mixed with the line output. A switch allows the output of the DACs to bypass the PHAT Stereo 3D enhancement.
Digital Audio Mode
The AD1881A supports time correlated I/O data format by presenting MIC data on the left channel of the ADC and the mono summation of left and right output on the right channel. The ADC is splittable; left and right ADC data can be sampled at different rates.
Power Management Modes
The AD1881A is designed to meet ACPI power consumption requirements through flexible power management control of all internal resources.
The AD1881A is designed with a Digital Audio Mode (DAM) that allows mixing of all analog inputs independent of the DAC output signal path. Mixed analog input signals may be sent to the ADCs for processing by the controller or the host, and may be used during simultaneous capture and playback at different sample rates.
-10-
REV. 0
AD1881A
Indexed Control Registers
Reg Num 00h 02h 04h 06h Name Reset Master Volume Reserved Master Volume Mono D15 X MM X MMM D14 SE4 X X X D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 X X X D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0410h
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X X X X X X X X X X X X X X X
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h X X X X X X X X 8000h
MMV MMV MMV MMV MMV 4 2 X 2 X 1 X 0 X
08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 26h 28h 2Ah 2Ch/ (7Ah)* 32h / (78h)* 34h 5ah 70h 72h 74h
Reserved PC Beep Volume Phone In Volume MIC Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain Reserved General Purpose 3D Control Power-Down Cntrl/Stat Extended Audio ID Extended Audio Stat/Ctrl PCM DAC Rate (SR1)
X PCM PHM MCM LM CVM VM AM OM X IM X POP X EAPD ID1 X SR15
X X X X X X X X X X X X X X X ID0 X SR14
X X X X X X X X X X X X 3D X PR5 X X SR13
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X M20 X X X X X X X X
X X X X X X X X X X X X X X X X X SR5
X
X 8000h 8008h
PCV3 PCV2 PCV1 PCV0 X PHV4 PHV3 PHV2 PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h RLV4 RLV3 RLV2 RLV1 RLV0 RCV4 RCV3 RCV2 RCV1 RCV0 RVV4 RVV3 RVV2 RVV1 RVV0 RAV4 RAV3 RAV2 RAV1 RAV0 ROV4 ROV3 ROV2 ROV1 ROV0 X X X X X X X X SR4 X RS2 RS1 RS0 8808h 8808h 8808h 8808h 8808h 0000h 8000h X 0000h 0000h 000Xh 0001h 0000h BB80h
LLV4 LLV3 LLV2 LLV1 LLV0 X LCV4 LCV3 LCV2 LCV1 LCV0 X LVV4 LVV3 LVV2 LVV1 LVV0 X LAV4 LAV3 LAV2 LAV1 LAV0 X LOV4 LOV3 LOV2 LOV1 LOV0 X X X X X X PR4 X X SR12 X LS2 LS1 LS0 X
LIM3 LIM2 LIM1 LIM0 X X X X PR3 X X SR11 X X X PR2 X X SR10 X MIX X PR1 X X SR9 X MS X PR0 X X SR8 X
RIM3 RIM2 RIM1 RIM0 X X DP3 REF X X SR3 X X DP2 ANL X X SR2 X X DP1 DAC X X SR1 X X DP0 ADC VRA VRA SR0
LPBK X X X X X SR7 X X X X SR6
PCM ADC Rate (SR0)
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
Reserved Vendor Reserved**
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
X ..
Reserved Serial Configuration
X SLOT 16
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X 7X0Xh
76h
Misc. Control Bits
DAC Z
LPMI X X F6 T6 F5 T5
DAM
DMS
DLSR X
ALSR MOD SRX EN 10D7 S6
SRX 8D7 S5
X
X
DRSR X
ARSR
0404h
7Ch 7Eh
Vendor ID1 Vendor ID2
F7 T7
F4 T4
F3 T3
F2 T2
F1 T1
F0 T0
S7
S4
S3
S2
S1
S0
4144h 5348h
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *Indicates Aliased register for AD1819, AD1819A backward compatibility. **Vendor Reserved registers should not be written.
REV. 0
-11-
AD1881A
Reset (Index 00h)
Reg Name Num 00h Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 D9 ID9 D8 D8 ID8 D7 D7 ID7 D6 D6 ID6 D5 D5 ID5 D4 D4 ID4 D3 D3 ID3 D2 D2 ID2 D1 D1 ID1 D0 D0 ID0 Default 0410h
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1881A based on the following: Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated MIC PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out/True Line-Level Out Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1881A 0 0 0 0 1 0 0 0 0 0
SE[4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
Reg Num 02h Name Master Volume D15 MM MM D14 X D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0] MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Master Volume Mute. When this bit is set to "1," the channel is muted. MM 0 0 0 1 xMV5 . . . xMV0 00 0000 01 1111 11 1111 xx xxxx Function 0 dB Attenuation -46.5 dB Attenuation -94.5 dB Attenuation - dB Attenuation
Master Volume Mono (Index 06h)
Reg Num 06h Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Master Volume MMM X Mono
X
X
X
X
X
X
X
X
X
MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[4:0] MMM
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Mono Master Volume Mute. When this bit is set to "1," the channel is muted.
-12-
REV. 0
AD1881A
PC Beep Register (Index 0Ah)
Reg Num 0Ah Name PC_BEEP Volume D15 PCM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 D6 D6 D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 8000h
PCV3 PCV2 PCV1 PCV0 X
PCV[3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from 0 dB to a maximum attenuation of -45 dB. The PC Beep is routed to Left and Right Line outputs even when the RESET pin is asserted. This is so that Power on Self-Test (POST) codes can be heard by the user in case of a hardware problem with the PC. PC Beep Mute. When this bit is set to "1," the channel is muted. PCM 0 0 1 PCV3 . . . PCV0 0000 1111 xxxx Function 0 dB Attenuation -45 dB Attenuation - dB Attenuation
PCM
Phone Volume (Index 0Ch)
Reg Num 0Ch Name Phone Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 D6 D6 D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0] PHM
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Phone Mute. When this bit is set to "1," the channel is muted.
MIC Volume (Index 0Eh)
Reg Name Num 0Eh D15 D14 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 M20 D5 D5 X D4 D4 MCV4 D3 D3 MCV3 D2 D2 MCV2 D1 D1 MCV1 D0 D0 MCV0 Default 8008h
Mic Volume MCM X
MCV[4:0] M20
MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Microphone 20 dB Gain Block 0 = Disabled; Gain = 0 dB. 1 = Enabled; Gain = 20 dB. MIC Mute. When this bit is set to "1," the channel is muted.
MCM
Line In Volume (Index 10h)
Reg Name Num 10h D15 D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 RLV4 D3 D3 RLV3 D2 D2 RLV2 D1 D1 RLV1 D0 D0 RLV0 Default 8808h
LM Line InVolume LM
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0] LM
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to "1," the channel is muted.
REV. 0
-13-
AD1881A
CD Volume (Index 12h)
Reg Name Num 12h D15 D14 D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
CD Volume CVM X
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to "1," the channel is muted.
Video Volume (Index 14h)
Reg Name Num 14h D15 D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Video Volume VM VM
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0] VM
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Video Mute. When this bit is set to "1," the channel is muted.
AUX Volume (Index 16h)
Reg Name Num 16h Aux Volume D15 AM AM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0] AM
Right Aux. Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Aux. Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Aux. Mute. When this bit is set to "1," the channel is muted.
PCM Out Volume (Index 18h)
Reg Name Num 18h PCM Out Volume D15 OM OM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," the channel is muted.
Volume Table (Index 0Ch to 18h)
MM 0 0 0 1
x4 . . . x0 00000 01000 11111 xxxxx
Function +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain
-14-
REV. 0
AD1881A
Record Select Control Register (Index 1Ah)
Reg Name Num 1Ah D15 D14 X D13 X D12 X D11 X D10 LS2 D9 D9 LS1 D8 D8 LS0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 RS2 D1 D1 RS1 D0 D0 RS0 Default 0000h
Record Select X
RS[2:0] LS[2:0]
Right Record Select Left Record Select.
Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to MIC in. RS2 . . . RS0 0 1 2 3 4 5 6 7 LS2 . . . LS0 0 1 2 3 4 5 6 7
Record Gain (Index 1Ch)
Reg Name Num 1Ch Record Gain D15 IM IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 D9 LIM1 D8 D8 LIM0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 RIM3 D2 D2 RIM2 D1 D1 RIM1 D0 D0 RIM0 Default 8000h
Right Record Source MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN Left Record Source MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN
RIM[3:0] LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Input Mute. 0 = Unmuted, 1 = Muted or - dB gain. IM 0 0 1 xIM3 . . . xIM0 1111 0000 xxxxx Function +22.5 dB Gain 0 dB Gain - dB Gain
REV. 0
-15-
AD1881A
General Purpose Register (Index 20h)
Reg Name Num 20h General Purpose D15 POP D14 X D13 3D 3D D12 X D11 X D10 X D9 D9 MIX D8 D8 MS MS D7 D7 LPBK D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 X Default 0000h
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default value is 0000h which is all off. LPBK MS Loopback Control. ADC/DAC Digital Loopback Mode MIC Select 0 = MIC1. 1 = MIC2. Mono Output Select 0 = Mix. 1 = MIC. 3D PHAT Stereo Enhancement 0 = PHAT Stereo is off. 1 = PHAT Stereo is on. PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-3D PCM out paths are mutually exclusive). 0 = pre-3D. 1 = post-3D.
MIX
3D
POP
3D Control Register (Index 22h)
Reg Name Num 22h 3D Control D15 X D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 DP3 D2 D2 DP2 D1 D1 DP1 D0 D0 DP0 Default 0000h
DP[2:0]
Depth Control. Sets 3D "Depth" PHAT Stereo enhancement according to table below. DP3 . . . DP0 0000 0001 . . 1110 1111 Depth 0% 6.67% . . 93.33% 100%
-16-
REV. 0
AD1881A
Subsection Ready Register (Index 26h)
Reg Name Num 26h Power-Down Cntrl/Stat D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 X D4 D4 X D3 D3 REF D2 D2 ANL D1 D1 D0 D0 Default
EAPD X
PR5 PR4 PR3 PR2 PR1 PR0 X
DAC ADC N/A
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1881A subsections. If the bit is a one, then that subsection is "ready." Ready is defined as the subsection able to perform in its nominal state. ADC DAC ANL REF PR[5:0] ADC section ready to transmit data. DAC section ready to accept data. Analog gain, attenuators and mute blocks, and mixers ready. Voltage References, VREF and VREFOUT up to nominal level. AD1881A Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can either be up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. EAPD External Audio Amp Power Down. Available when programmed as an AC'97 codec. 0 = Pin 47 set to LO state (default). 1 = Pin 47 set to HI state. Power-Down State ADC Power-Down DAC Power-Down ADC and DAC Power-Down Mixer Power-Down ADC + Mixer Power-Down DAC + Mixer Power-Down ADC + DAC + Mixer Power-Down Standby
Extended Audio ID Register (Index 28h)
Reg Name Num 28h Extended Audio ID D15 ID1 D14 ID0 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA Default 0000h
PR5 0 0 0 0 0 0 0 1
PR4 0 0 0 0 0 0 0 1
PR3 0 0 0 0 0 0 0 1
PR2 0 0 0 1 1 1 1 1
PR1 0 1 1 0 0 1 1 1
PR0 1 0 1 0 1 0 1 1
Note: The Extended Audio ID is a read only register. VRA ID[1:0] Variable Rate Audio. VRA = 1 enables Variable Rate Audio. ID1, ID0 is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
REV. 0
-17-
AD1881A
Extended Audio Status and Control Register (Index 2Ah)
Reg Name Num 2Ah Extended Audio St/Ctrl D15 X D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA Default 0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. VRA Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling.
PCM DAC Rate Register (Index 2Ch)
Reg Num Name D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
2Ch/(7Ah) PCM DAC Rate
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48k. SR[15:0] Writing to this register allows programming of the sampling frequency from 8 kHz (1B80h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed or to 7.040 kHz if a rate less than 7.040 kHz is programmed. For all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg Num 32h/(78h) Name PCM ADC Rate D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48k. SR[15:0] Writing to this register allows programming of the sampling frequency from 8 kHz (1B80) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed, or to 7.040 kHz if a rate less than 7.040 kHz is programmed. For all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned.
Serial Configuration (Index 74h)
Reg Num 74h Name Serial Configuration D15 SLOT 16 16 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7x0xh
Note: This register is not reset when the reset register (register 00h) is written. SLOT16 Enable 16-bit slots. DRQEN and DxRQx are retained only for compatibility with the AD1819. New controller designs should use the VRA bit in register 2Ah and the request bits in the status address slot instead. If your system uses only a single AD1881A, you can ignore the register mask and the slave 1/slave 2 request bits. If you write to this register, write ones to all of the register mask bits. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
-18-
REV. 0
AD1881A
Miscellaneous Control Bits (Index 76h)
Reg Name Num 76h Misc Control Bits D15 DAC Z D14 LPMI X D13 D12 X D11 D10 D9 D9 D8 D8 ALSR D7 D7 MOD EN EN D6 D6 D5 D5 D4 D4 X D3 D3 X D2 D2 DRSR D1 D1 X D0 D0 ARSR Default 0404h
DAM DMS DLSR X
SRX10 SRX8 D7 D7 D7 D7
ARSR
ADC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DAC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). Multiply SR1 rate by 8/7. Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set. Modem filter enable (left channel only). Change only when DACs are powered down. ADC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DAC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). Digital Mono Select. 0 = Mixer 1 = Left DAC and Right DAC. Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output. Low Power Mixer. Keeps CD to LINE_OUT alive for notebook applications. Zero fill (vs. repeat) if DAC is starved for data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
DMS
DAM LPMIX DACZ
Sample Rate 0 (Index 78h)
Reg Name Num 78h D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80H
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48k. SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
REV. 0
-19-
AD1881A
Sample Rate 1 (Index 7Ah)
Reg Name Num 7Ah D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48k. SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch-7Eh)
Reg Name Num 7Ch Vendor ID1 D15 F7 F7 D14 F6 F6 D13 F5 F5 D12 F4 F4 D11 F3 F3 D10 F2 F2 D9 D9 F1 F1 D8 D8 F0 F0 D7 D7 S7 S7 D6 D6 S6 S6 D5 D5 S5 S5 D4 D4 S4 S4 D3 D3 S3 S3 D2 D2 S2 S2 D1 D1 S1 S1 D0 D0 S0 S0 Default 4144h
S[7:0] F[7:0]
Reg Num 7Eh Name
This register is ASCII encoded to "A." This register is ASCII encoded to "D."
D15 D14 T6 T6 D13 T5 T5 D12 T4 T4 D11 T3 T3 D10 T2 T2 D9 D9 T1 T1 D8 D8 T0 T0 D7 D7 REV7 D6 D6 REV6 D5 D5 REV5 D4 D4 REV4 D3 D3 REV3 D2 D2 REV2 D1 D1 REV1 D0 D0 REV0 Default 5348h
Vendor ID2 T7 T7
T[7:0] REV[7:0]
This register is ASCII encoded to "S." Revision Register field.
These bits are read-only and should be verified before accessing vendor defined features.
AD1881A/AD1881 USER VISIBLE DIFFERENCES
* Pin 48 is now MODE pin, no longer CHAIN_CLK. * AD1881 chaining mode not supported. * LSB of register 7Eh is 48h instead of 40h.
-20-
REV. 0
AD1881A
APPLICATIONS CIRCUITS
The AD1881A has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figure 9. Reference designs for the AD1881A are available and may be obtained by contacting your local Analog Devices' sales representative or authorized distributor.
+5AVDD +3.3DVDD
10 F 100nF 100nF 100nF 100nF
10 F
10k 1k 100nF
100nF
AVSS1 AVSS2 AVDD1 AVDD2 PC_BEEP
DVDD1 DVDD2 DVSS1 DVSS2
0.33 F 0.33 F 0.33 F MIC1 0.33 F MIC2 0.33 F CD_R 0.33 F CD_L 0.33 F CD_GND 0.33 F VIDEO_L 0.33 F VIDEO_R 0.33 F AUX_L 0.33 F AUX_R 0.33 F PHONE_IN 0.33 F
7 MONO_OUT
LINE_IN_R LINE_IN_L RESET SDATA_OUT SDATA_IN SYNC BIT_CLK 47 47pF DIGITAL CONTROLLER
AD1881A
CS0 CS1 EAPD 47 MODE 48 1F LNLVL_OUT_L 39 47k 1F LNLVL_OUT_R 41 47k FILT_L FILT_R CX3D
34
EAPD
1F
36 LINE_OUT_R
1F LINE_OUT_L 47k 47k 47k AFILT1 AFILT2 RX3D VREFOUT
33 28
VREF
27
XTL_IN
XTL_OUT
100nF 270pF NP0 270pF NP0 1F 1F 47nF 2.25VDC 100nF 10 F TANT 600Z ANALOG GROUND NOTE: FOR OPTIMAL PERFORMANCE USE A REGULATED ANALOG POWER SUPPLY. 22pF NP0
24.576MHz 22pF NP0
DIGITAL GROUND
Figure 9. Recommended One Codec Application Circuit
REV. 0
-21-
AD1881A
CD-ROM CONNECTIONS
The CD-ROM audio output level should be investigated; typical drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input (1 V rms range). The recommended circuit is basically a group of divide-by-two voltage dividers as shown on Figure 10. The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimum noise cancellation, this section of the divider should have approximately half the impedance of the right and left channel section dividers.
VOLTAGE DIVIDER R1 4.7k 1 2 3 4 R3 2.7k R4 2.7k C2 + 0.33 F R2 4.7k C1 + 0.33 F
TO CODEC CD_L INPUT
HEADER FOR CD ROM AUDIO (LGGR)
TO CODEC CD_GND_REF INPUT
R5 4.7k R6 4.7k
C3 + 0.33 F
TO CODEC CD_R INPUT
Figure 10. Typical CD-ROM Audio Connections
LINE_IN, AUX AND VIDEO INPUT CONNECTIONS
Most of these audio sources also generate 2 V rms audio level and require a -6 dB input voltage divider to be compatible with the Codec inputs. Figure 11 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components should be configured and selected to provide adequate RF immunity and emissions control.
LINE/AUX/VIDEO INPUT J1 1 2 3 4 5 L1 600Z C2 470pF R3 4.7k R4 4.7k C4 + 0.33 F TO CODEC LEFT CHANNEL INPUT EMC COMPONENTS L2 600Z C1 470pF VOLTAGE DIVIDER R1 4.7k R2 4.7k AC-COUPLING C3 + 0.33 F TO CODEC RIGHT CHANNEL INPUT
Figure 11. LINE_IN, AUX, and Video Input Connections
MICROPHONE CONNECTIONS
The AD1881A contains an internal microphone preamp with 20 dB gain, in most cases a direct microphone connection as shown in Figure 12 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 13. In either case the microphone bias can be derived from the Codec's internal reference (VREFOUT) using a 2.2 k resistor. For the preamp circuit, the VREFOUT signal can also provide the mid-point bias for the amplifier. To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). Additional filtering may be required to limit the microphone response to the audio band of interest.
-22-
REV. 0
AD1881A
EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT L1 600Z AC-COUPLING L2 600Z C2 470pF C1 470pF C3 0.22 F TO CODEC MIC1 OR MIC2 INPUT
R1 2.2k
FROM CODEC VREFOUT
Figure 12. Recommended Microphone Input Connections
PREAMP EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT R3 L1 600Z AC-COUPLING L2 600Z C2 470pF C1 470pF C3 0.22 F AD8531 MIC BIAS R1 2.2k FROM CODEC VREFOUT 0.22 F R2 10k 100k +5AVDD U1 AC-COUPLING C3 TO CODEC MIC1 OR MIC2 INPUT
Figure 13. Microphone with Additional External Preamp (20 dB Gain)
LINE OUTPUT CONNECTIONS
The AD1881A Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they can be connected to an external load. After the ac-coupling, a minimal resistive load is recommended to keep the capacitors properly biased and reduce click and pop when plugging stereo equipment into the output jack. The capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99 specification for PCs, testing must be performed with a 10 k load, therefore a 1 F value is recommended to achieve less than -3 dB roll-off at 20 Hz.
EMC COMPONENTS STEREO LINE_OUT JACK J1 L1 600Z C2 470pF R1 47k R2 47k L2 600Z C1 470pF AC-COUPLING C1 + 1F C2 + 1F FROM CODEC LINE_OUT_R
FROM CODEC LINE_OUT_L
NOTE: IF AN OUTPUT AMP IS USED, THE AC-COUPLING CAP VALUES WILL DEPEND ON THE AMP DESIGN.
Figure 14. Recommended LINE_OUT Connections
USING AN EXTERNAL HEADPHONE/POWER AMP
The SSM2250 Power Amplifier is an ideal companion for the AD1881A. The amplifier can provide up to 250 mW output in stereo mode and up to 1.5 W into a mono speaker connected in a bridge-tied load (BTL) configuration. The SM2250 has a mode control pin that can be used to switch between the stereo output mode and the mono BTL speaker. Figure 15 shows a typical PC configuration where the SSM2250 drives a set of stereo headphones or external speakers, as well as an internal mono speaker. One of the normalizing pins on the stereo jack senses the stereo plug insertion and automatically switches from driving the internal mono speaker to driving the external stereo load. To conserve power, the SSM2250 can be shut down by the EAPD pin on the AD1881A, using proper power management software. This is particularly important for portable applications. In shutdown mode, the SSM2250 consumes only 60 A.
REV. 0
-23-
AD1881A
5AVDD R1 100k
U1
R2 49.9k
C1 1F
C2 100 F R3 1k
F1 FB 600Z C3 470pF
STEREO HP/SPEAKER OUTPUT J1
AD1881A
EAPD/CHAIN_IN R4 49.9k LINE_OUT_L C4 0.33 F LIN_OUT_R R6 49.9k C7 0.33 F NC U2 SSM2250RU NC C5 100 F
F2 R5 1k FB 600Z C6 470pF LS1 INTERNAL MONO SPEAKER STEREO 3.5mm JACK
LEFT IN
LEFT OUT/BLT VDO BTL+ BYPASS RIGHT OUT NC C8 0.1 F
SHUTDOWN SE/BTL GND RIGHT IN NC
MONO_OUT
4
NC = NO CONNECT
R7 49.9k
Figure 15. Using the SSM2250 Amplifier for Stereo and Mono Output
GROUNDING AND LAYOUT
To reduce noise and emissions, Analog Devices recommends a split ground plane as shown in Figure 16. The purpose of splitting the ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system's logic. All the analog circuitry should be placed on the analog ground plane area. For reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some point, ideally a small bridge under or near the Codec should be provided. A 0 resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet EMC requirements.
DIGITAL GROUND PLANE
CONNECT SPLIT GROUND PLANES AT OR NEAR CODEC.
PIN 1
ISOLATION TRENCH
AD1881A
ANALOG GROUND PLANE
Figure 16. Recommended Split Ground Plane
ANALOG POWER SUPPLY
To minimize audio noise, the Codec analog power supply (AVDD) should be well decoupled and regulated. In PC systems it is recommended that the analog supply be derived from the 12 V PC power supply using a localized linear voltage regulator. Preferably, the analog power supply should be connected to the Codec's analog section using a ferrite bead.
-24-
REV. 0
AD1881A
U1 12V C1 10 F + C2 0.1 F R1 0 IN LM78M05CP OUT 3 + L1 600Z C3 0.1 F C4 10 F 5AVDD
Figure 17. Recommended Regulator Circuit for Analog Power Supply
If a power plane layer is being used in the system design, it is recommended that the analog power plane for the Codec also be split (mirroring the analog ground plane). In this case, the analog power supply ferrite bead should bridge the isolation trench, close to the Codec location.
REV. 0
2
GND
-25-
AD1881A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING PLANE 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
48 1
0.354 (9.00) BSC 0.276 (7.0) BSC
37 36
TOP VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05) 0 - 7
0 MIN 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.020 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
-26-
REV. 0
PRINTED IN U.S.A.
C3747-8-4/00 (rev. 0) 00752
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)

▲Up To Search▲

Price & Availability of AD1881

	To Download AD1881 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .